/*
Copyright (c) [2022] [shawnping]
[masm-assistant] is licensed under Mulan PSL v2.
You can use this software according to the terms and conditions of the Mulan PSL v2. 
You may obtain a copy of Mulan PSL v2 at:
         http://license.coscl.org.cn/MulanPSL2 
THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.  
See the Mulan PSL v2 for more details.
*/

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/* eslint-disable @typescript-eslint/naming-convention */

import { IReservedWord, IReservedWordGroup, MASMType } from '../Base/baseInterfaceFile';
import { register_Qword, register_XMM } from './reservedWrods_registers';

const directive_Const_LanguageType: IReservedWord[] = [
    { word: 'c', brief: 'The __C__ language calling convention is used to call C funcation.' },
    { word: 'stdcall', brief: 'The __STDCALL__ calling convention is used to call Win32 API functions.' },
    { word: 'fortran', brief: 'The __FORTRAN__ calling convention is used to call FORTRAN functions.' },
    { word: 'syscall', brief: 'System calling.' },
    { word: 'pascal', brief: 'The __PASCAL__ language calling convention is used to call PASCAL funcation.' },
    { word: 'basic', brief: 'The __BASIC__ language calling convention is used to call BASIC funcation.' },
];

const directive_Const_Boolean = {
    true: <IReservedWord>{ word: 'true', brief: 'Boolean value __TRUE__.' },
    false: <IReservedWord>{ word: 'false', brief: 'Boolean value __FALSE__.' }
};

const directive_Const_MemoryModel: IReservedWord[] = [
    { word: 'tiny', brief: 'Tiny-model programs run only under MS-DOS. Tiny model places all data and code in a single segment. Therefore, the total program file size can occupy no more than 64K. The default is near for code and static data items; you cannot override this default. However, you can allocate far data dynamically at run time using MS-DOS memory allocation services.\nTiny model produces MS-DOS .COM files. Specifying __.MODEL__ tiny automatically sends the /__TINY__ argument to the linker. Therefore, the /AT argument is not necessary with __.MODEL__ tiny. However, /AT does not insert a __.MODEL__ directive. It only verifies that there are no base or pointer fixups, and sends /__TINY__ to the linker.' },
    { word: 'small', brief: 'Small model supports one data segment and one code segment. All data and code are near by default.' },
    { word: 'compact', brief: 'Compact model supports multiple data segments and a single code segment.' },
    { word: 'medium', brief: 'Medium model supports multiple code and single data segments' },
    { word: 'large', brief: 'Large model supports multiple code and multiple data segments.' },
    { word: 'huge', brief: 'Huge model implies individual data items larger than a single segment, but the implementation of huge data items must be coded by the programmer. Since the assembler provides no direct support for this feature, huge model is essentially the same as large model.' },
    { word: 'flat', brief: 'The flat memory model is a nonsegmented configuration available in 32-bit operating systems. It is similar to tiny model in that all code and data go in a single 32-bit segment.To write a flat model program, specify the .386 or .486 directive before .MODEL FLAT. All data and code (including system resources) are in a single 32-bit segment. The operating system automatically initializes segment registers at load time; you need to modify them only when mixing 16-bit and 32-bit segments in a single application. CS, DS, ES, and SS all occupy the supergroup FLAT. Addresses and pointers passed to system services are always 32-bit near addresses and pointers.' },
];

const directive_Const_Stackpoint: IReservedWord[] = [
    { word: 'nearstack', brief: 'The __NEARSTACK__ keyword places the stack segment in the group __DGROUP__ along with the data segment. The __.STARTUP__ directive then generates code to adjust __SS:SP__ so that __SS__ (Stack Segment register) holds the same address as __DS__ (Data Segment register). If you do not use __.STARTUP__, you must make this adjustment or your program may fail to run. (For information about startup code, see “Starting and Ending Code with __.STARTUP__ and __.EXIT__,” later in this chapter.) In this case, you can use __DS__ to access stack items (including parameters and local variables) and __SS__ to access near data. Furthermore, since stack items share the same segment address as near data, you can reliably pass near pointers to stack items.' },
    { word: 'farstack', brief: 'The __FARSTACK__ setting gives the stack a segment of its own. That is, __SS__ does not equal __DS__.That is, __SS__ does not equal __DS__. The default stack type, __NEARSTACK__, is a convenient setting for most programs. Use __FARSTACK__ for special cases such as memory-resident programs and dynamic-link libraries when you cannot assume that the caller’s stack is near. You can use the predefined symbol __@Stack__ to determine if the stack location is __DGROUP__ (for near stacks) or __STACK__ (for far stacks).' },
];

const directive_Const_NearFar: IReservedWord[] = [
    { word: 'near', brief: '32-bit memory model.' },
    { word: 'far', brief: '32-bit memory model.' },
];

const directive_Const_Distance: IReservedWord[] = [
    { word: 'near16' },
    { word: 'near32' },
    { word: 'far16' },
    { word: 'far32' },
];

const directive_Const_DataType: IReservedWord[] = [
    { word: 'byte', brief: 'Allocates unsigned numbers from 0 to 255.' },
    { word: 'db', brief: 'Allocates unsigned numbers from 0 to 255.' },
    { word: 'sbyte', brief: 'Allocates signed numbers from -128 to +127.' },
    { word: 'word', brief: 'Allocates unsigned numbers from 0 to 65,535 (64K).' },
    { word: 'dword', brief: 'Allocates and optionally initializes a double word (4 bytes) of storage for each initializer. DWORD is a synonym of DD.' },
    { word: 'dd', brief: 'Allocates and optionally initializes a double word (4 bytes) of storage for each initializer. DWORD is a synonym of DD.' },
    { word: 'dw', brief: 'Allocates unsigned numbers from 0 to 65,535 (64K).' },
    { word: 'sword', brief: 'Allocates signed numbers from -32,768 to +32,767.' },
    { word: 'fword', brief: 'Allocates 6-byte (48-bit) integers. These values are normally used only as pointer variables on the 80386/486 processors. ' },
    { word: 'df', brief: 'Allocates 6-byte (48-bit) integers. These values are normally used only as pointer variables on the 80386/486 processors. ' },
    { word: 'qword', brief: 'Allocates 8-byte integers used with 8087-family coprocessor instructions.' },
    { word: 'sqword', brief: 'Allocates and optionally initializes 8 signed bytes of storage for each initializer. Also can be used as a type specifier anywhere a type is legal.' },
    { word: 'dq', brief: 'Allocates 8-byte integers used with 8087-family coprocessor instructions.' },
    { word: 'tword', brief: 'Allocates 10-byte (80-bit) integers if the initializer has a radix specifying the base of the number.' },
    { word: 'dt', brief: 'Allocates 10-byte (80-bit) integers if the initializer has a radix specifying the base of the number.' },
    { word: 'oword', brief: 'Used as a type specifier when an 16-byte data type is required.' },
    { word: 'real4', brief: 'Allocates and optionally initializes a single-precision (4-byte) floating-point number for each initializer.' },
    { word: 'real8', brief: 'Allocates and optionally initializes a double-precision (8-byte) floating-point number for each initializer.' },
    { word: 'real10', brief: 'Allocates and optionally initializes a double-precision (10-byte) floating-point number for each initializer.' },
    { word: 'mmword', brief: 'Used for 64-bit multimedia operands with MMX and SSE (XMM) instructions.' },
    { word: 'xmmword', brief: 'Used for 128-bit multimedia operands with MMX and SSE (XMM) instructions.' },
    { word: 'ymmword', brief: 'Used for 256-bit multimedia operands with Intel Advanced Vector Extensions (AVX) instructions.' },
    { word: 'zmmword', brief: 'Used for 512-bit multimedia operands with Intel Advanced Vector Extensions (AVX) instructions.' },
];

const directive_Const_ContextItem: IReservedWord[] = [
    { word: 'assumes', brief: 'Saves segment register information.' },
    { word: 'radix', brief: 'Saves current default radix.' },
    { word: 'listing', brief: 'Saves listing and CREF information.' },
    { word: 'cpu', brief: 'Saves current CPU and processor.' },
    { word: 'all', brief: 'All of the above.' }
];

const directive_Const_FlagName: IReservedWord[] = [
    { word: 'zero?', brief: 'Status of zero flag. Used only within __.IF__, __.WHILE__, or __.REPEAT__ blocks and evaluated at run time, not at assembly time.' },
    { word: 'sign?', brief: 'Status of zero flag. Used only within __.IF__, __.WHILE__, or __.REPEAT__ blocks and evaluated at run time, not at assembly time.' },
    { word: 'parity?', brief: 'Status of zero flag. Used only within __.IF__, __.WHILE__, or __.REPEAT__ blocks and evaluated at run time, not at assembly time.' },
    { word: 'carry?', brief: 'Status of zero flag. Used only within __.IF__, __.WHILE__, or __.REPEAT__ blocks and evaluated at run time, not at assembly time.' },
    { word: 'overflow?', brief: 'Status of zero flag. Used only within __.IF__, __.WHILE__, or __.REPEAT__ blocks and evaluated at run time, not at assembly time.' },
];

const directive_Const_Operator:IReservedWord[]=[
    { word: 'abs',brief:'Get absolute value.'},
    { word: 'addr',brief:'Get address of Variable.'},
    { word: 'and', brief:'Returns the result of a bitwise __AND__ operation for **expression1** and **expression2**.'},
    { word: 'dup',brief:'Specifies **count** number of declarations of **initialvalue**.'},
    { word: 'eq',brief:'Returns true (-1) if **expression1** equals **expression2**, or returns false (0) if it does not.'},
    { word: 'ge',brief:'Returns true (-1) if **expression1** is greater than or equal to **expression2**, or returns false (0) if it is not.'},
    { word: 'gt',brief:'Returns true (-1) if **expression1** is greater than or equal to **expression2**, or returns false (0) if it is not.'},
    { word: 'high',brief:'Returns the high 8 bits of the low 16 bits of **expression**. MASM expressions are 64-bit values.'},
    { word: 'high32',brief:'Returns the high 32 bits of **expression**. MASM expressions are 64-bit values.'},
    { word: 'highword',brief:'Returns the high 16 bits of the low 32 bits of **expression**. MASM expressions are 64-bit values.'},
    { word: 'imagerel',brief:'Returns the image relative offset of **expression**.'},
    { word: 'le',brief:'Returns true (-1) if **expression1** is less than or equal to **expression2**, or returns false (0) if it is not.'},
    { word: 'length',brief:'Returns true (-1) if **expression1** is less than or equal to **expression2**, or returns false (0) if it is not.'},
    { word: 'lengthof',brief:'Returns the number of data objects in **variable**.'},
    { word: 'low',brief:'Returns the low 8 bits of **expression**. MASM expressions are 64-bit values.'},
    { word: 'low32',brief:'Returns the low 32 bits of **expression**. MASM expressions are 64-bit values.'},
    { word: 'lowword',brief:'Returns the low 16 bits of **expression**. MASM expressions are 64-bit values.'},
    { word: 'lroffset',brief:'Returns the offset of **expression**. Same as __OFFSET__, but it generates a loader resolved offset, which allows Windows to relocate code segments.'},
    { word: 'lt',brief:'Returns true (-1) if **expression1** is less than **expression2**, or returns false (0) if it is not.'},
    { word: 'mask',brief:'Returns a bit mask in which the bits in **recordfieldname** or **record** are set and all other bits are cleared.'},
    { word: 'mod',brief:'Returns the integer value of the remainder (modulo) when dividing **expression1** by **expression2**.'},
    { word: 'ne',brief:'Returns true (-1) if **expression1** does not equal **expression2**, or returns false (0) if it does.'},
    { word: 'not',brief:'Returns **expression** with all bits reversed.'},
    { word: 'offset',brief:'Returns the offset into the relevant segment of **expression**.'},
    { word: 'opattr',brief:'Returns a word defining the mode and scope of **expression**. The low byte is identical to the byte returned by __.TYPE__. The high byte contains additional information.'},
    { word: 'or',brief:'Returns the result of a bitwise OR operation for **expression1** and **expression2**.'},
    { word: 'ptr',brief:'The first operator forces the expression to be treated as having the specified type. The second operator specifies a pointer to type.'},
    { word: 'seg',brief:'Returns the segment of **expression**.'},
    { word: 'shl',brief:'Returns the result of shifting the bits of expression left count number of bits.'},
    { word: '.type',brief:'operator __.TYPE__'},
    { word: 'sectionrel',brief:'Returns the section relative offset of expression relative to the section containing the target in the final executable.'},
    { word: 'short',brief:'Sets the type of label to short. All jumps to label must be short (within the range -128 to +127 bytes from the jump instruction to label).'},
    { word: 'shr',brief:'Returns the result of shifting the bits of expression right count number of bits.'},
    { word: 'size',brief:'Returns the number of bytes in variable allocated by the first initializer.'},
    { word: 'sizeof',brief:'Returns the number of bytes in variable or type.'},
    { word: 'this',brief:'Returns an operand of specified type whose offset and segment values are equal to the current location counter value.'},
    { word: 'type',brief:'Returns the type of expression.'},
    { word: 'width',brief:'Returns the width in bits of the current recordfieldname or record.'},
    { word: 'xor',brief:'Returns the result of a bitwise __XOR__ operation for **expression1** and **expression2**.'},
];

const directive_Const_MapType: IReservedWord[] = [
    { word: 'all', brief: '__ALL__ (/Cu) specifies case insensitivity for identifiers and converts all identifier names to uppercase. ' },
    { word: 'none', brief: '__NONE__ (or /Cx) causes internal symbol recognition to be case sensitive and causes the case of identifiers in the .OBJ file to be the same as specified in the __EXTERNDEF__, __PUBLIC__, or __COMM__ statement. ' },
    { word: 'notpublic', brief: '__NOTPUBLIC__ (or /Cp). It specifies case insensitivity for internal symbol recognition and the same behavior as __CASEMAP:NONE__ for case of identifiers in .OBJ files.' },
];

const directive_Const_OffsetType: IReservedWord[] = [
    { word: 'group', brief: '__GROUP__, the default, generates fixups relative to the group (if the label is in a group). ' },
    { word: 'segment', brief: '__SEGMENT__ sets the defaults for fixups to be segment-relative (compatible with MASM 5.1). ' },
    { word: 'flat', brief: '__FLAT__ causes fixups to be relative to a flat frame. (The .386 mode must be enabled to use FLAT.) ' },
];

const directive_Const_SegAlign: IReservedWord[] = [
    { word: 'byte', brief: 'Next available byte address.' },
    { word: 'word', brief: 'Next available word address.' },
    { word: 'dword', brief: 'Next available doubleword address.' },
    { word: 'para', brief: 'Next available paragraph address (16 bytes per paragraph). Default.' },
    { word: 'page', brief: 'Next available page address (256 bytes per page).' },
];

const directive_Const_SegAttrib: IReservedWord[] = [
    { word: 'private', brief: 'Does not combine the segment with segments from other modules, even if they have the same name. Default.' },
    { word: 'public', brief: 'Concatenates all segments having the same name to form a single, contiguous segment. ' },
    { word: 'stack', brief: ' Concatenates all segments having the same name and causes the operating system to set SS:00 to the bottom and SS:SP to the top of the resulting segment. Data initialization is unreliable, as discussed following. ' },
    { word: 'common', brief: 'Overlaps segments. The length of the resulting area is the length of the largest of the combined segments. Data initialization is unreliable, as discussed following. ' },
    { word: 'memory', brief: 'Used as a synonym for the __PUBLIC__ **combine** type.' },
    { word: 'AT', brief: 'Assumes **address** as the segment location. An __AT__ segment cannot contain any code or initialized data, but is useful for defining structures or variables that correspond to specific far memory locations, such as a screen buffer or low memory.  You cannot use the __AT__ **combine** type in protected-mode programs. ' },
];

const directive_Const_SegSize: IReservedWord[] = [
    { word: 'use16', brief: 'Segment size 16-bit mode.' },
    { word: 'use32', brief: 'Segment size 32-bit mode.' },
    { word: 'flat', brief: 'Segment size 32-bit mode.' }
];

const directive_Const_TitleType: IReservedWord[] = [
    { word: 'subtitle', brief: 'Defines the listing subtitle. Same as __SUBTTL__.' },
    { word: 'subttl', brief: 'Defines the listing subtitle. Same as __SUBTITLE__.' },
    { word: 'title', brief: 'Defines the program listing title.' },
];

const directive_Const_Ovisibility: IReservedWord[] = [
    { word: 'public', brief: '__PROC__ Visibility is public' },
    { word: 'private', brief: '__PROC__ Visibility is private.' },
    { word: 'export', brief: '__EXPORT__ Visibility is exoprt.' },

];
const directive_Const_Characteristics: IReservedWord[] = [
    { word: 'info' },
    { word: 'read' },
    { word: 'write' },
    { word: 'execute' },
    { word: 'shared' },
    { word: 'nopage' },
    { word: 'nocache' },
    { word: 'discard' },
];

let labelDistance:IReservedWord[]=[];

export const directives: IReservedWordGroup[] = [
    {
        groupName: 'Processor',
        casemap: false,
        isUsing: true,
        keywords: [
            { word: '.8086', brief: 'Enables assembly of 8086 instructions (and the identical 8088 instructions); disables assembly of instructions introduced with later processors. Also enables 8087 instructions. This is the default mode for processors.', commit: ['.'] },
            { word: '.8087', brief: 'Enables assembly of 8087 instructions; disables assembly of instructions introduced with later coprocessors. This is the default mode for coprocessors.', commit: ['.'] },
            { word: '.186', brief: 'Enables assembly of instructions for the 80186 processor; disables assembly of instructions introduced with later processors. Also enables 8087 instructions. ', commit: ['.'] },
            { word: '.286', brief: 'Enables assembly of nonprivileged instructions for the 80286 processor; disables assembly of instructions introduced with later processors. Also enables 80287 instructions. ', commit: ['.'] },
            { word: '.286p', brief: 'Enables assembly of all instructions (including privileged) for the 80286 processor; disables assembly of instructions introduced with later processors.  Also enables 80287 instructions. ', commit: ['.'] },
            { word: '.287', brief: 'Enables assembly of instructions for the 80287 coprocessor; disables assembly of instructions introduced with later coprocessors.', commit: ['.'] },
            { word: '.386', brief: 'Enables assembly of nonprivileged instructions for the 80286 processor; disables assembly of instructions introduced with later processors. Also enables 80287 instructions. ', commit: ['.'] },
            { word: '.386P', brief: 'Enables assembly of all instructions (including privileged) for the 80386 processor; disables assembly of instructions introduced with later processors.  Also enables 80387 instructions. ', commit: ['.'] },
            { word: '.387', brief: 'Enables assembly of instructions for the 80387 coprocessor.', commit: ['.'] },
            { word: '.486', brief: 'Enables assembly of nonprivileged instructions for the 80486 processor.', commit: ['.'] },
            { word: '.486p', brief: 'Enables assembly of all instructions (including privileged) for the 80486 processor.', commit: ['.'] },
            { word: '.586', brief: 'Enables assembly of nonprivileged instructions for the Pentium processor. (32-bit MASM only.)', commit: ['.'] },
            { word: '.586p', brief: 'Enables assembly of all instructions (including privileged) for the Pentium processor. (32-bit MASM only.)', commit: ['.'] },
            { word: '.686', brief: 'Enables assembly of nonprivileged instructions for the Pentium Pro processor. (32-bit MASM only.)', commit: ['.'] },
            { word: '.686p', brief: 'Enables assembly of all instructions (including privileged) for the Pentium Pro processor. (32-bit MASM only.)', commit: ['.'] },
            { word: '.k3d', brief: 'Enables assembly of K3D instructions. (32-bit MASM only.)', commit: ['.'] },
            { word: '.mmx', brief: 'Enables assembly of MMX or single-instruction, multiple data (SIMD) instructions. (32-bit MASM only.)', commit: ['.'] },
            { word: '.xmm', brief: 'Enables assembly of Internet Streaming SIMD Extension instructions. (32-bit MASM only.)', commit: ['.'] },
        ]
    },
    {
        groupName: 'Simplified Segment',
        casemap: false,
        isUsing: true,
        keywords: [
            {
                key: { word: '.model', brief: 'Initializes the program memory model. (32-bit MASM only.)' },
                paraList: [
                    {
                        isOptional: false,
                        paraObj: {
                            paraType: 'Memory Model',
                            trigger: [' '],
                            enumPara: directive_Const_MemoryModel
                        }
                    },
                    {
                        isOptional: true,
                        paraObj: {
                            paraType: 'Language Type',
                            trigger: [','],
                            enumPara: directive_Const_LanguageType
                        }
                    },
                    {
                        isOptional: true,
                        paraObj: {
                            paraType: 'Language Type',
                            trigger: [','],
                            enumPara: directive_Const_Stackpoint
                        }
                    }
                ]
            },
            { word: '.startup', brief: 'Generates program start-up code. (32-bit MASM only.)', commit: ['.'] },
            { word: '.code', brief: '(32-bit MASM only.) When used with __.MODEL__, indicates the start of a code segment.', commit: ['.'] },
            { word: '.const', brief: 'When used with __.MODEL__, starts a constant data segment (with segment name __CONST__).', commit: ['.'] },
            { word: '.dosseg', brief: 'Orders the segments according to the MS-DOS segment convention: __CODE__ first, then segments not in __DGROUP__, and then segments in __DGROUP__. (32-bit MASM only.)', commit: ['.'] },
            { word: '.stack', brief: 'When used with __.MODEL__, defines a stack segment (with segment name STACK). The optional size specifies the number of bytes for the stack (default 1,024). The __.STACK__ directive automatically closes the stack statement. (32-bit MASM only.)', commit: ['.'] },
            { word: '.exit', brief: 'Generates termination code. (32-bit MASM only.)', commit: ['.'] },
            { word: '.data', brief: '(32-bit MASM only.) When used with __.MODEL__, starts a near data segment for initialized data (segment name _DATA).Syntax', commit: ['.'] },
            { word: '.data?', brief: '(32-bit MASM only.) When used with __.MODEL__, starts a near data segment for uninitialized data (segment name _BSS).', commit: ['.'] },
            { word: '.fardata', brief: 'When used with __.MODEL__, starts a far data segment for initialized data (segment name FAR_DATA or name). (32-bit MASM only.)', commit: ['.'] },
            { word: '.fardata?', brief: 'When used with __.MODEL__, starts a far data segment for initialized data (segment name FAR_DATA or name). (32-bit MASM only.)', commit: ['.'] },
        ]
    },
    {
        groupName: 'Conditional Error',
        casemap: false,
        isUsing: true,
        keywords: [
            { word: '.err', brief: 'Generates an error.', commit: ['.'] },
            { word: '.erre', brief: 'Generates an error if *expression* is false (0).', commit: ['.'] },
            { word: '.errnz', brief: 'Generates an error if *expression* is true (nonzero).', commit: ['.'] },
            { word: '.errb', brief: 'Generates an error if *textitem* is blank.', commit: ['.'] },
            { word: '.errnb', brief: 'Generates an error if *textitem* not is blank.', commit: ['.'] },
            { word: '.errdef', brief: 'Generates an error if *name* is a previously defined label, variable, or symbol.', commit: ['.'] },
            { word: '.errndef', brief: 'Generates an error if *name* is not a previously defined label, variable, or symbol.', commit: ['.'] },
            { word: '.errdif', brief: 'Generates an error if the text items are different.', commit: ['.'] },
            { word: '.errdifi', brief: 'Generates an error if the text items are different.', commit: ['.'] },
            { word: '.erridn', brief: 'Generates an error if the text items are identical.', commit: ['.'] },
            { word: '.erridni', brief: 'Generates an error if the text items are identical.', commit: ['.'] },
            { word: '.err1', brief: '.ERR block evaluated on every assembly pass if __OPTION:SETIF2__ is __TRUE__.', commit: ['.'] },
            { word: '.err2', brief: '.ERR block evaluated on every assembly pass if __OPTION:SETIF2__ is __TRUE__.', commit: ['.'] },
        ],
    },
    {
        groupName: 'Code Labels',
        casemap: false,
        isUsing: true,
        keywords: [
            { word: 'align', brief: 'The __ALIGN__ directive aligns the next data element or instruction on an address that is a multiple of its parameter. The parameter must be a power of 2 (for example, 1, 2, 4, and so on) that is less than or equal to the segment alignment.', commit: ['.'] },
            { word: 'org', brief: 'Sets the location counter to *expression*.' },
            { word: 'even', brief: 'Aligns the next variable or instruction on an even byte.' },
            {
                key:{word:'label',brief:'Creates a new label by assigning the current location-counter value and the given *qualifiedType* to name.'},
                paraList:[
                    {
                        isOptional:true,
                        paraObj:{
                            paraType:'Distance',
                            trigger:[' '],
                            enumPara:labelDistance.concat(directive_Const_NearFar,directive_Const_Distance)
                        }
                    }
                ]
            }
        ],
    },
    {
        groupName: 'Conditional Assembly',
        casemap: false,
        isUsing: true,
        keywords: [
            { word: 'if', brief: 'Grants assembly of ifstatements if expression1 is true (nonzero) or elseifstatements if *expression1* is false (0) and *expression2* is true.' },
            { word: 'if1', brief: '__IF1__ block is evaluated on first assembly pass.__IF2__ block is evaluated on every assembly pass if __OPTION:SETIF2__ is __TRUE__.' },
            { word: 'if2', brief: '__IF1__ block is evaluated on first assembly pass.__IF2__ block is evaluated on every assembly pass if __OPTION:SETIF2__ is __TRUE__.' },
            { word: 'ife', brief: 'Grants assembly if *expression* is false (0).' },
            { word: 'ifb', brief: 'Grants assembly if textitem is blank.' },
            { word: 'ifnb', brief: 'Grants assembly if textitem is not blank.' },
            { word: 'ifdef', brief: 'Grants assembly if name is a previously defined label, variable, or symbol.' },
            { word: 'ifndef', brief: 'Grants assembly if name has not been defined.' },
            { word: 'ifdif', brief: 'Grants assembly if the text items are different.' },
            { word: 'ifdifi', brief: 'Grants assembly if the text items are different.' },
            { word: 'ifidn', brief: 'Grants assembly if the text items are identical.' },
            { word: 'ifidni', brief: 'Grants assembly if the text items are identical.' },
            { word: 'else', brief: 'Marks the beginning of an alternate block within a conditional block.' },
            { word: 'elseif', brief: 'Combines __ELSE__ and __IF__ into one statement.' },
            { word: 'elseif1', brief: '__ELSEIF__ block evaluated on every assembly pass if __OPTION:SETIF2__ is __TRUE__.' },
            { word: 'elseif2', brief: '__ELSEIF__ block evaluated on every assembly pass if __OPTION:SETIF2__ is __TRUE__.' },
            { word: 'elseife', brief: 'Grants assembly if expression is false (0).' },
            { word: 'elseifb', brief: 'Grants assembly if textitem is blank.' },
            { word: 'elseifnb', brief: 'Grants assembly if textitem is not blank.' },
            { word: 'elseifdef', brief: 'Grants assembly if name is a previously defined label, variable, or symbol.' },
            { word: 'elseifndef', brief: 'Grants assembly if name has not been defined.' },
            { word: 'elseifdif', brief: 'Grants assembly if the text items are different.' },
            { word: 'elseifdifi', brief: 'Grants assembly if the text items are different.' },
            { word: 'elseifidn', brief: 'Grants assembly if the text items are identical.' },
            { word: 'elseifidni', brief: 'Grants assembly if the text items are identical.' },
        ],
    },
    {
        groupName: 'x64 directive',
        casemap: false,
        isUsing: true,
        keywords: [

            { word: '.allocstack', brief: 'Generates a __UWOP_ALLOC_SMALL__ or a __UWOP_ALLOC_LARGE__ with the specified size for the current offset in the prologue.' },

            {
                key: { word: '.pushframe', brief: 'Generates a __UWOP_PUSH_MACHFRAME__ unwind code entry. If the optional __CODE__ keyword is specified, the unwind code entry is given a modifier of 1. Otherwise the modifier is 0.' },
                paraList:[
                    {
                        isOptional:true,
                        paraObj: {
                            paraType:'code',
                            trigger:[' '],
                            enumPara:[
                                {word:'code',commit:[' ']}
                            ]
                        }
                    }
                ]
            },

            {
                key: { word: '.savexmm128', brief: 'Generates either a __UWOP_SAVE_XMM128__ or a __UWOP_SAVE_XMM128_FAR__ unwind code entry for the specified XMM register and offset using the current prologue offset. MASM will choose the most efficient encoding.' },
                paraList:[
                    {
                        isOptional:false,
                        paraObj: {
                            paraType:'xmm register',
                            trigger:[' '],
                            enumPara:register_XMM
                        }
                    }
                ]
            },

            { word: '.endprolog', brief: 'Signals the end of the prologue declarations.' },

            {
                key: { word: '.pushreg', brief: 'Generates a __UWOP_PUSH_NONVOL__ unwind code entry for the specified register number using the current offset in the prologue.' },
                paraList:[
                    {
                        isOptional:false,
                        paraObj: {
                            paraType:'x64 registers',
                            trigger:[' '],
                            enumPara:register_Qword
                        }
                    }
                ]
            },

            {
                key: { word: '.setframe', brief: 'Fills in the frame register field and offset in the unwind information using the specified register (reg) and offset (offset). The offset must be a multiple of 16 and less than or equal to 240. This directive also generates a UWOP_SET_FPREG unwind code entry for the specified register using the current prologue offset.' },
                paraList:[
                    {
                        isOptional:false,
                        paraObj: {
                            paraType:'x64 registers',
                            trigger:[' '],
                            enumPara:register_Qword
                        }
                    }
                ]
            },

            {
                key: { word: '.savereg', brief: 'Generates either a UWOP_SAVE_NONVOL or a UWOP_SAVE_NONVOL_FAR unwind code entry for the specified register (reg) and offset (offset) using the current prologue offset. MASM will choose the most efficient encoding.' },
                paraList:[
                    {
                        isOptional:false,
                        paraObj: {
                            paraType:'x64 registers',
                            trigger:[' '],
                            enumPara:register_Qword
                        }
                    }
                ]
            }
        ],
    },
    {
        groupName: 'Boolean',
        casemap: false,
        isUsing: true,
        keywords: [
            directive_Const_Boolean.true,
            directive_Const_Boolean.false,
        ],
    },
    {
        groupName: 'Flag Name',
        casemap: false,
        isUsing: true,
        keywords: directive_Const_FlagName
    },
    {
        groupName:'Operator',
        casemap:false,
        isUsing:true,
        keywords:directive_Const_Operator
    },
    {
        groupName:'Data Type',
        casemap:false,
        isUsing:true,
        keywords:directive_Const_DataType
    }
];